mSG-DMA IRQ could not be cleared

[Altera_Forum]

Hi, 

I encountered the case that the IRQ bit in mSG-DMA status could not be cleared. I supplied descriptors for the MM-ST direction. The transfer size is small as 256Bytes. Every descriptor generates an interruption. Since the transfer size is small, interruptions may occur while the interruption service is executing. The procedures after an interruption occurs are : (1). Clear the interruption in the processor so that the next interruption can be pended until the interruption service finished. (2). Clear the IRQ in bit<9> of the mSG-DMA status. (3). Do the interruption service program. After clearing the IRQ bit, I read back the status. In many cases,  the IRQ has been cleared or the IRQ is still set to 1 and the next interruption is pended by the processor(The processor'sinterruption status register indicates the interruption pending). But in rare cases, although the IRQ is cleared, the IRQ is still 1 and no interruption is pended. As the result, Since I configured the interruption to MSI of PCIe, no interruption occurred after that and the IRQ keeps 1. The PCIe legacy interruption system detects interruptions since it is a level interruption and the PCIe controller keeps interrupted until the IRQ in the mSG-DMA status is cleared. I cleared the IRQ until it gets 0 and the interruptions occurs in the situation and I counted the number of IRQ-NOT-CLEARED. The ratio was 19 times in the 444405 interruptions(0.0043%). I suspect that if the IRQ is cleared at the same time of the next interruption, IRQ does not go to 0 but keeps 1 and no MSI interruption TLP is sent. The large size of the DMA never causes above since it (probably) interrupts out of the interruption service.  Does anyone experience the similar phenomenon or know any errata or application note describing about the IRQ clearance related above?  Thank you in advance.

[Altera_Forum]

--- Quote Start ---  Hi, I encountered the case that the IRQ bit in mSG-DMA status could not be cleared.   --- Quote End ---    First question: Are you only send as many "valids" and bytes as the DMA expects, or are you overrunning or underfilling the buffer? Second: Are you doing single transfers, or are you doing descriptor polling or park mode or anything else fancy?

[Altera_Forum]

--- Quote Start ---  First question: Are you only send as many "valids" and bytes as the DMA expects, or are you overrunning or underfilling the buffer? Second: Are you doing single transfers, or are you doing descriptor polling or park mode or anything else fancy?  --- Quote End ---    I read out the fill level to calculate the number of descriptors that can be sent. I do not think overrun occurred. No parks are used. I just wanted to measure the transfer performance and to know the relation between the size per a descriptor and the total performance. So I sent simple but interruption enabling descriptors as many as the FIFO was available and repeated that. If the FIFO gets full, the task sleeps until an interruption occurrs.

[Altera_Forum]

--- Quote Start ---  I read out the fill level to calculate the number of descriptors that can be sent. I do not think overrun occurred. No parks are used. I just wanted to measure the transfer performance and to know the relation between the size per a descriptor and the total performance. So I sent simple but interruption enabling descriptors as many as the FIFO was available and repeated that. If the FIFO gets full, the task sleeps until an interruption occurrs.  --- Quote End ---    I forgot the answers. No overrun and no underfill. Just single transfer and no parks.

[Altera_Forum]

Fascinating. Have you tried a SignalTap on the valid and interrupt lines?

[Altera_Forum]

--- Quote Start ---  Fascinating. Have you tried a SignalTap on the valid and interrupt lines?  --- Quote End ---    derim, thank you for your interest.  No, I have not yet. I wished an Altera engineer replied to my post but not yet. The Altera description for IRQ is just "Set when an interrupt condition occurs" in UG-01085. They must have more detailed design information.