mSGDMA Data Loss Between Descriptors (Streaming to Memory-Mapped)

[M_T]

We're experiencing consistent data loss when using Altera's mSGDMA IP on an Arria 10 device for streaming data from the FPGA fabric to DDR memory (accessible by the HPS).

Issue Description

• Data is being lost between consecutive descriptor transfers
• Typically missing ~80 bytes between transfers, occasionally less (~32 bytes)
• The data loss occurs even when multiple descriptors are queued in the descriptor FIFO
• The loss pattern seems somewhat consistent but not entirely predictable

System Configuration

• Arria 10 SoC with HPS running Yocto Linux (based on GSRD)
• mSGDMA Configuration:
  • Mode: Streaming to Memory-Mapped
  • Data width: 32-bit
  • Data FIFO depth: 1024
  • Descriptor FIFO depth: 128
  • Maximum burst count: 16
  • Maximum transfer length: 1024 bytes
  • Packet mode: Disabled
  • Prefetch: Disabled
  • Bus frequency: 200MHz (HPS running at 1GHz)

Additional Details

• We're using a driver based on https://github.com/pavelfpl/altera_msgdma_st
• The data source is a test logic that produces streams of consecutive 32-bit numbers
• The source pushes blocks of numbers once every few microseconds
• Data transfers are working but we're consistently losing data between descriptors
• No error bits are set in the status register after transfers
• We're not currently using packet mode, park reads, or prefetch features
  
  Has anyone encountered similar issues or have suggestions for what might be causing this data loss?
  
  
  Thanks for any insights.
  
  

[Jeet14]

Hi,

Please try with this below link example.

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/fpga-to-hps-bridges-design-example.html

Regards

Tiwari

[Jeet14]

Hi

Let me know if you have any query on this.

[M_T]

Thank you for your response.

We have successfully resolved the data loss issue by ensuring the FPGA properly processes the READY signal.

We still have identified several critical issues in our FPGA implementation:

1. Interrupts are not triggered until all descriptors in the FIFO queue have been completely processed.
2. Even when implementing polling for responses, they remain unavailable until all FIFO descriptors are fully consumed.
3. When reading the responses, the length is zero, although the data is correctly transferred to the DDR memory.
4. Our development is within a Linux environment, requiring compatible software solutions.
5. The current Altera driver lacks proper user-space application interfacing capabilities. (Reference: https://github.com/altera-opensource/linux-socfpga/blob/socfpga-6.1.55-lts/drivers/dma/altera-msgdma.c)
6. When attempting to populate the descriptor FIFO using timer-based methods, we observe periodic system halts lasting tens of milliseconds.
7. As a workaround, we're currently processing single descriptors sequentially, which provides acceptable but suboptimal data throughput rates.
8. When trying to use F2SDRAM instead of F2H bus, the mSGDMA IP becomes stuck after the first transfer with the "Resetting" bit enabled in the Status register.

I would appreciate your expertise in addressing any of these challenges to improve our system performance.

[JingyangTeh_Altera]

Hi

Sorry for the late response.

I am Jingyang and will be helping out on this issue.

When you mention the interrupt is not triggerd. Could you check the Transfer Complete IRQ Enable is set in the descriptor?

Could you also check if the reset signal is being triggered after the first transfer?

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh