I am trying to transfer data using the mSGDMA QSYS cores in Quartus 17 from on-chip memory on an Arria V FPGA to a buffer allocated in Windows through PCIe and Jungo’s Windriver. Typically, the core works exactly as expected, however, part of the way through the DMA transmissions I am seeing a block of all zeroes or just junk data before seeing correct data again.
The data is streaming into the FPGA and being processed and stored into the on-chip memory then transferred via DMA to the Windows PC. We do not have enough on-chip memory to hold all of the data so the code is setup to repeatedly do individual DMA transfers once a page in the memory is filled with a short window of time between each transfer. Has anyone seen this before or have any clue what could be causing this?