FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 Discussions

mem_clk and mem_clk_n

Altera_Forum
Honored Contributor II
‎05-08-2010 06:59 PM
1,379 Views

Why the mem_clk signals are declared as bidirectional(inout) in rtl code of DDR/DDR2 memory IP?

0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎05-11-2010 04:55 AM
475 Views

Its for a self calibrating mimic path. Check out this link 

 

http://www.altera.com/support/kdb/solutions/rd08162007_376.html
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.