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Altera_Forum
Honored Contributor I
939 Views

mem_clk and mem_clk_n

Why the mem_clk signals are declared as bidirectional(inout) in rtl code of DDR/DDR2 memory IP?

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Altera_Forum
Honored Contributor I
35 Views

Its for a self calibrating mimic path. Check out this link 

 

http://www.altera.com/support/kdb/solutions/rd08162007_376.html
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