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I've implemented a CAM/RAM combination in my design.
both CAM and RAM uses shared bus for their writing values and input (this is more common). I want to use separated input & writing bus for both.I want an implementation with independent bus for each input data and writing data. is it possible to modifying Altera's CAM? if not is there a free VHDL/Verilog/... code available?Link Copied
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Have a look at the thread
http://www.alteraforum.com/forum/showthread.php?t=2153 there is a post by Rysc in which he attached a CAM code.
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