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Altera_Forum
Honored Contributor I
786 Views

mpeg ts interface ip core

hi; 

i'm working in hardware imlementaion of an DVB_ASI interface project. i downloaded the latest ip from altera site and i didn't find the ip core of the mpeg ts interface (i think it's an mpeg-2 encoder) which generate the input of the ASI core (i attached a little scheme describing the input of an ASI_tx core: tx_data,tx_en and tx_clk). 

could anyone help me to get the ip core of the block which generate those signals? 

thanks
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9 Replies
Altera_Forum
Honored Contributor I
43 Views

Well this is my IP(haven't tested the code, so look for those bugs), it will serve as input to your ASI module 

 

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity mpeg_generator is port( reset : in std_logic; clk : in std_logic; enable : in std_logic; data_vld : out std_logic; data : out std_logic_vector(7 downto 0) ); end entity; architecture rtl of mpeg_generator is signal byte_counter : integer range 0 to 255; begin process(reset, clk) begin if(reset = '1')then byte_counter <= 0; data_vld <= '0'; data <= x"00"; elsif(rising_edge(clk))then if(enable = '1')then byte_counter <= byte_counter + 1; data_vld <= '1'; case byte_counter is when 0 => data <= x"47"; when 1 => data <= x"1F"; when 2 => data <= x"FF"; when 3 => data <= x"10"; when 4 to 187 => data <= std_logic_vector(to_unsigned(byte_counter,8)); when others => data_vld <= '0'; data <= x"00"; end case; end if; end if; end process; end rtl;
Altera_Forum
Honored Contributor I
43 Views

thanks for your reply, but i have a question:did ALTERA have any solution for an mpeg encoder generating those signals for the ASI-TX? if yes where i can find the ip? (specially the file .bsf ) and finally which signals we should input in this encoder? 

thank you
Altera_Forum
Honored Contributor I
43 Views

I am sorry I don't know what altera has on offer, you can check their site for IP cores. The term mpeg_encoder refers to something more involved, it is encoding video data by compression techniques - too involved in fact. 

 

I think you just need parallel mpeg stream(SPI). So the above code can be used and you can add it to your project, no problem of copyright either!
Altera_Forum
Honored Contributor I
43 Views

thank you again for your attention about my subject. in your description of your bloc generating the 8 bit and the data valid, you don't mentioned an mpeg ts signals in the input? i though that we should have a mpeg ts packet in the input (188 or 204 bytes like it mentioned in the standard EN 50083-9)???????????? 

and finally about your description...the bit enable,which bloc generate it?
Altera_Forum
Honored Contributor I
43 Views

The above code generates 188 bytes packet. The sync word and other header bytes are defined. The rest of bytes are given just count values for you to check in the final testing of your ASI converter(i.e. if you recover your ASI back you should be able to see if it is working correctly). 

 

The enable is there if you need it otherwise set it to '1'; 

the data represents ts packets. 

 

The above code generates two outputs, data and data_valid and these together with clk are to be connected to your ASI block, then you need another 270MHz clock for your ASI block.  

 

You can generate symbol(BSF) if you compile the code in quartus. Alternatively you can interface by code to your ASI bsf, up to you.
Altera_Forum
Honored Contributor I
43 Views

sorry if i persist, but what do you means by "The above code generates 188 bytes packet"? your code generate a parallel 8bit data and a data_valid bit is it?

Altera_Forum
Honored Contributor I
43 Views

Basically we need 8 bit data. then a sequence of 188 such bytes is called an mpeg packet. A sequence of 204 bytes is also legal. you can do that by altering my code slightly to make data_valid high for further 16 bytes. 

You don't ouput an entire packet in one go... 

 

I have added void time slots from count 188 to 255 as a test for data_valid. 

 

Thus the module produces continuously packet after packet size 188 with a gap of 68 clocks.
Altera_Forum
Honored Contributor I
43 Views

thanks kaz for your attention.. 

hope u good day
Altera_Forum
Honored Contributor I
43 Views

@zabarotta  

Why did you download the IP ? Isn't it come with Quartus II Web Edition by default ?
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