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Altera_Forum
Honored Contributor I
840 Views

on-chip memory timing diagram

Hi I need have to continuosly update sections of an onchip memory on a regular basis as quickly as possible. I'm using a 125MHz clock. My problem is the datasheet of the onchip MF is quite vague on the minimum time required to set-up the addr and the read/wr pulses to guarantee an accurate read/write. Can any1 direct me as to how to get this information or if there are any rules of thumb to follow to guarantee that i get my data in/out as fast as I can. 

thanks
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Altera_Forum
Honored Contributor I
50 Views

TimeQuest checks it all. You don't need to view block ram as external chip.

Altera_Forum
Honored Contributor I
50 Views

Additionally, 

use registers at input/output/address. they are there at no extra cost. 

Many designers add a further register between block outputs and logic fabric to improve speed across...
Altera_Forum
Honored Contributor I
50 Views

hi Kaz, thanks for the tips but even if i've got registers at the i/p ,o/p and address how lond do i need to wait to update them with the next data? i've got tons of inputs all trying to access the RAM via one address port. Is there some form of acknowledge that can tell me if one gets written so i can send the next one? if not how long shd i pulse it to be sure the data is written before writing the next one?

Altera_Forum
Honored Contributor I
50 Views

It sounds like you didn't yet understand the synchronous operation of the on-chip RAM. All control signals as well as input data and addresses are registered on the rising edge of the respective clock.  

 

In so far the timing is defined very strictly, you have to keep the setup and hold times (as said, the Quartus timing analysis will check it in most cases) for these signals, a handshake signal won't serve a purpose. Basically you can write and read new data for each clock cycle.
Altera_Forum
Honored Contributor I
50 Views

ok, thanks

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