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Hi,
As I understand it, you have some inquiries related to the FFT IP. For your information, it is recommended for you to perform a Modelsim simulation with your targeted configuration and input data to verify the expected output. Also, Modelsim simulation will help to isolate any functional problem prior to hardware testing.
By the way, just to ensure we are on the same page, would you mind to further elaborate on the following:
1. What is the Quartus edition that you are using? I understand from the screenshot that you are using version 18.1.
2. Mind further elaborate one the "Q17 format" that you are referring to?
Please let me know if there is any concern. Thank you.
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Hi,
Thank you for the reply
Like you said i am doing simulation in modelsim and
1. Version of Quartus prime is 18.1.
2. In fixed point representation, Q17 format means out of 18 bits of data, MSB bit(18th bit) will be the sign bit and rest of the data will be fractional bits. So if i give the data like this what would be the output format?
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Hi,
Thanks for your clarification. As I look at your IP configuration, you seems to be pruning the output width to 18 bits. With this, configuration, the format should be Q17 as well. You can perform a Modelsim simulation to further verify on this. Note that normally after the FFT operation, there will be bit growth. With pruning to 18 bits output, you should expect magnitude truncation as well as low magnitude samples being pruned off.
Please let me know if there is any concern. Thank you.
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Hi,
As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
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