FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6021 Discussions

pausing PCI HIP transactions with avalon mm waitrequest

Altera_Forum
Honored Contributor II
789 Views

Hi, i'm trying to know how the  

PCI HIP responds to an incoming waitrequest from an module connected to the BAR[0]. I have an avalon mm slave connected to BAR[0] and i wanna know if an asserted waitrequest would implicitly pause the PCI host (a X86) from writing into my module's registers. Will a waitrequest on my slave component come up through the PCI HIP as a pause signal like# TRDY ? Do i have to manage the pauses myself or is this an automatic mechanism. 

I hope i'm being clear, 

Thanks
0 Kudos
0 Replies
Reply