pcie can't perform memory write trasaction from endpoint to rootpoint

[Altera_Forum]

Hi, 

 I generated tow pcie cores by pcie compiler, one as rootpoint and another as endpoint. I configured the rootpoint and endpoint well. I can perform the memory write transaction from rootpoint to endpoint now. But when I performed a memory write transaction from endpoint to rootpoint, I received nothing in the rootpoint side.  The configuration transactions I used are the same as the endpoint Testbench generated by the pcie compiler.  Does it need some configuration special for the rootpoint forwarding the memory write transaction from endpoint ?  Thanks,

[Altera_Forum]

According to the trace of the test_out in the trasaction layer, I see that The root port recieved unsupported TLPs. Is it the problem of the device number and bus number ?

[Altera_Forum]

I generate a memory read request from root port to the end port. The end port gets the read requeset and returns a completion to the root port. And in the rx_st interface of the root port, we get the completion. It likes that the bus id and device id are correct. 

 We can't send the memory write request from end port to the root port, maybe I didn't configure the bar of the root port and the Memory Base and Memory Limit registers correctly :mad:  Does anyone know how to configure the registers related to the address routing ?  Thanks,  Long

[Altera_Forum]

yeah i think the problem is the root bar addresses are not programmed correctly and also the base memory and limit registers. I recommend you to check the simulation of root port that megafunction generates. In that simulation you can see the mandatory registers program before the mem transactions. Also check the command register of endpoint and rootport are programmed correctly or not

[Altera_Forum]

Thanks for your reply. My system works. I find it is just the problem of the base memory and limit registers. 

I have no prefetchable bar for the endpoint. But it likes that, It need to set a value in the prefetchable memory limit and prefetchable memory base, although there is no prefetchable memory.