FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

pcie interface

Altera_Forum
Honored Contributor II
1,171 Views

we need to generate MSI interrupt to the application driver from the PCIe.The signal which we observed for generating interrupt in PCIe is "app_msi_req". Kindly could someone help us,if we have to generate the request from FPGA the signal is followed by few other signal like "app_msi_tc" , "msi_app_num". We are not able to get any info regarding this signals....could some one help us on this issue.....we need to write rtl to drive this values..what are the values to be driven????

0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
468 Views

This information is defined in the PCIe User Guide - see link below: 

http://www.altera.com/literature/ug/ug_pci_express.pdf#page=124  

 

The app_msi_num[4:0] vector is to identify which of the 32 possible MSI interrupts you are asserting. The app_msi_tc[2:0] is identify which traffic class to send the MSI interrupt. 

 

I recommend getting a copy of the PCIe spec and digging in a bit on MSI, then come back to the PCIe User Guide. It will make more sense.
0 Kudos
Reply