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port assignment in vhdl

Altera_Forum
Honored Contributor II
1,269 Views

hi all, i am new to VHDL and this question may be easy for you.my question is: 

how can i assign value to an in port?my port declaration is: 

DATA_I : in std_logic_vector(7 downto 0); 

 

i am trying to assign a value above but simulator says that a port can not be driven.do you have any idea?
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5 Replies
Altera_Forum
Honored Contributor II
80 Views

An in port represents an external input to your logic. It can't be driven internally. What do you want to achieve?

Altera_Forum
Honored Contributor II
80 Views

thanks for replies.i am trying to debug my VHDL program, i use a simulator for this.how can i give values to in port for debuging?

Altera_Forum
Honored Contributor II
80 Views

In a simulator, the design under test will be instantiated in a testbench. There you can drive input and inout ports and also force internal signals, if necessary.

Altera_Forum
Honored Contributor II
80 Views

thank you, i will try to do UUT issue in the simulator.

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