port assignment in vhdl

[Altera_Forum]

hi all, i am new to VHDL and this question may be easy for you.my question is: 

how can i assign value to an in port?my port declaration is: DATA_I : in std_logic_vector(7 downto 0);  i am trying to assign a value above but simulator says that a port can not be driven.do you have any idea?

[Altera_Forum]

http://www.electronicdesignworks.com/advanced_digital_electronics/introduction/introduction.htm

[Altera_Forum]

An in port represents an external input to your logic. It can't be driven internally. What do you want to achieve?

[Altera_Forum]

thanks for replies.i am trying to debug my VHDL program, i use a simulator for this.how can i give values to in port for debuging?

[Altera_Forum]

In a simulator, the design under test will be instantiated in a testbench. There you can drive input and inout ports and also force internal signals, if necessary.

[Altera_Forum]

thank you, i will try to do UUT issue in the simulator.