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Altera_Forum
Honored Contributor I
721 Views

problem with the ALT2GXB IP place & route

Hi, 

 

I am very new to this altera tool & IP's ........ 

 

i am doing a project with the ALT2GXB IP for the high speed serial communication on stratix II gx board..... 

I generated the configured the IP using the Mega core of the altera...... 

then i went to the synthesis of the IP ,,,,,,, 

In the place & route I am getting the following error...... 

 

I know its a very simple error ....... 

but still wanted to ask here ........the error is as follows,,,,,,,,, 

 

Error: Input port CORECLK of GXB Transmitter channel "alt2gxb:alt2gxb_component|channel_tx[0].transmit" must be fed by output port CLKOUT of GXB Transmitter channel "alt2gxb:alt2gxb_component|channel_tx[0].transmit" because GXB Receiver and Transmitter channels in the same quad have the same clock rate 

 

 

Error: Input port CORECLK of GXB Receiver channel "alt2gxb:alt2gxb_component|channel_rec[0].receive" must be fed by output port CLKOUT of GXB Transmitter channel "alt2gxb:alt2gxb_component|channel_tx[0].transmit" because GXB Receiver and Transmitter channels in the same quad have the same clock rate 

 

 

the CLKOUT of the GXB transmitter channel must be connected to the coreclk right????? 

 

In that case the output of the same system is connected to the input right.......... 

 

 

Please let me know what I should do to solve it........
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2 Replies
Altera_Forum
Honored Contributor I
33 Views

Hi, 

 

I made a port map change in the code that is obtained from the mega core...... 

 

I mapped the rx_coreclk & the tx_coreclk to the tx_clkout of the system now the error is removed and i generated the programming file,,,,,,,,,,in the quartus design flow.......... 

 

Is this is correct ...........what i did..............
Altera_Forum
Honored Contributor I
33 Views

I have generated the ALT2GXB IP in the mega core .... 

now to check the functionality of the IP we should give  

the parallel data for the transmission and observe the received data. The parallel data should be given from a frame generator right.... 

Frame gererator means a RAM with some data that is read out in terms of words right....
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