Honored Contributor II
01-02-2013 03:40 PM
Hi,I need to generate an TSE solution to Cyclone IV GX, where the datapath is: Memory (internal in the beginning, DDR2 later) => SGDMA => TSE => PCS => PMA (GX tranceiver) => SFP module (copper and/or fibre). And the reverse. I have used several days trying to put this up, with little success. So far I have done the following: Generated QSYS system with minimalistic setup: NIOS+internalMEM+2*SGDMA+TSE+PLL+sysid+jtaguart. The QSYS generation works fine, with no errors. Then I have instantiated the system into a VHDL top-level file (FPGA pin names differ from QSYS pin names). Then I tried to understand the TSE UG for running TCL for the system, with failure (it tries to assign IO standard to default pins:TXP & RXP). I manually reassigned the IO standards to correct pins (fpga top-level pins). Then I included the QSYS generated SDC file into Quartus project (Assignments => settings => TimeQuest Timing Analyzer => File is added here). Then I created a small SDC file describing my clocks (50 MHz and 125 MHz), and deriving pll clocks. Ten I ran the Quartus "Start Compilation". Synthesis seems ok, but Timing Analysis shows lots of errors (Slack starting from -3.211 ns), tens of them. The TSE UG (June 2012) eg says in page 141 (8-1): "# Name the clocks that will be coming into the tse core named chaned from top level". I do not understand what Altera is trying to say with this. Also the SDC file gets rewritten every time I generate a new QSYS system. If I need to edit it (I don't know) I need to re-edit it after every QSYS generate command, right? *** So does anybody know what is the correct process flow to do this? Would be highly appreciated. BR, -Topi
Honored Contributor II
01-05-2013 12:08 AM
I studied the MegaWizard generated *.tcl and *.sdc files and found them being terrible quality.But it seems that the TimeQuest (and SDC file format in particular) restricts any good SW design practice on those files...
- The TCL file sets few to several assignments to several FPGA external pins, but uses default names for the ports, and does not use the path to the QSYS instance. This is easily overcome by manually entering needed assignments (e.g. with Assignment editor).
- The SDC file tries to generate clocks, which fails if all the QSYS clocks are not coming outside from the FPGA (no, you cannot use FPGA PLLs with the default file).
- The SDC file tries to generate clock groups (false paths between clock domains) and fails if the clock with proper naming convention are not found.