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process flow for generating NIOS + TSE

Honored Contributor II



I need to generate an TSE solution to Cyclone IV GX, where the datapath is: 


Memory (internal in the beginning, DDR2 later) => SGDMA => TSE => PCS => PMA (GX tranceiver) => SFP module (copper and/or fibre). 

And the reverse. 


I have used several days trying to put this up, with little success. 


So far I have done the following: 


Generated QSYS system with minimalistic setup: NIOS+internalMEM+2*SGDMA+TSE+PLL+sysid+jtaguart. 


The QSYS generation works fine, with no errors. 


Then I have instantiated the system into a VHDL top-level file (FPGA pin names differ from QSYS pin names). 


Then I tried to understand the TSE UG for running TCL for the system, with failure (it tries to assign IO standard to default pins:TXP & RXP). I manually reassigned the IO standards to correct pins (fpga top-level pins). 


Then I included the QSYS generated SDC file into Quartus project (Assignments => settings => TimeQuest Timing Analyzer => File is added here). 


Then I created a small SDC file describing my clocks (50 MHz and 125 MHz), and deriving pll clocks. 


Ten I ran the Quartus "Start Compilation". Synthesis seems ok, but Timing Analysis shows lots of errors (Slack starting from -3.211 ns), tens of them. 


The TSE UG (June 2012) eg says in page 141 (8-1): "# Name the clocks that will be coming into the tse core named chaned from top level". I do not understand what Altera is trying to say with this. 


Also the SDC file gets rewritten every time I generate a new QSYS system. If I need to edit it (I don't know) I need to re-edit it after every QSYS generate command, right? 




So does anybody know what is the correct process flow to do this? Would be highly appreciated. 


BR, -Topi
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Honored Contributor II

I studied the MegaWizard generated *.tcl and *.sdc files and found them being terrible quality.  


But it seems that the TimeQuest (and SDC file format in particular) restricts any good SW design practice on those files... 


  1. The TCL file sets few to several assignments to several FPGA external pins, but uses default names for the ports, and does not use the path to the QSYS instance. This is easily overcome by manually entering needed assignments (e.g. with Assignment editor). 


  2. The SDC file tries to generate clocks, which fails if all the QSYS clocks are not coming outside from the FPGA (no, you cannot use FPGA PLLs with the default file). 


  3. The SDC file tries to generate clock groups (false paths between clock domains) and fails if the clock with proper naming convention are not found. 



TimeQuest has derive_pll_clocks -command, which works perfectly, except for the minor detail that the name of the generated clock cannot be set by user. The TSE SDC file creates false paths between properly named clocks only, and automatically derived clocks do not meet this naming requirement. And I couldn't find any way to rename already generated clock to meet TSE SDC naming convention. 

And as far as I can see, there is no easy way out of this (for the poor engineer at Altera writing this SDC file and TSE documentation to avoid this situation). 

The only one I found out is to first run derive_pll_clocks, and then inspect the generated clokcs (report_clocks) and then comment the derive_pll_clocks and writing a bunch of create_generated_clock -lines with all the correct parameters (fortunately TimeQuest fires a warning if the parameters are not correct for the design). But this requires manually revisiting the SDC file every time the design had any changes in clocking. 


And the last annoying thing I found out that the SDC file generated by TSE MegaWizard says that the user need to modify the generated file to enter names and frequencies of several clocks, but if the QSYS system is later re-generated, all the changes to SDC file are lost. And the SDC file is not actually generated, but rewritten with constant template. So good practice could be copying off the TSE SDC file to a project root, and including that file into the project. Also note that the order of SDC files in the project (can be seen in Assignment => Settings => TimeQuest Timing Analyzer) is important, the TCL-syntaxed files are parsed in the order of the list. 


BR, -Topi
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