FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5950 Discussions

questions about clock frequency in DSP-BUILDER

Altera_Forum
Honored Contributor II
835 Views

Hi everyone:), 

 

I wish to use a really low clock frequency in DSP builder, say about 100HZ, it does not need to be very accurate. since PLL won't work. Here's my idea: 

 

1. in VHDL, it could be easily made by a counter and a reverse process, so I tried to import VHDL to the simulink, yet there's another problem: how to specify the clock signal in DSP builder to a signal inside the design ?:( 

 

2.If the first method doest not work, maybe a "enable" pulse generator is ok. is it like that I have to put some flip-flops in the circuit ? my design has many freedback paths, I'm not sure if the flip-flops would harm the feedback property.  

 

It there any reference design for a low frequency clock in DSP builder? that would be great. 

 

Sorry for the poor English, I would really appreciate any discussion 

 

Tony
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
98 Views

 

--- Quote Start ---  

Hi everyone:), 

 

I wish to use a really low clock frequency in DSP builder, say about 100HZ, it does not need to be very accurate. since PLL won't work. Here's my idea: 

 

1. in VHDL, it could be easily made by a counter and a reverse process, so I tried to import VHDL to the simulink, yet there's another problem: how to specify the clock signal in DSP builder to a signal inside the design ?:( 

 

2.If the first method doest not work, maybe a "enable" pulse generator is ok. is it like that I have to put some flip-flops in the circuit ? my design has many freedback paths, I'm not sure if the flip-flops would harm the feedback property.  

 

It there any reference design for a low frequency clock in DSP builder? that would be great. 

 

Sorry for the poor English, I would really appreciate any discussion 

 

Tony 

--- Quote End ---  

 

 

 

the second method would take extreme simulation time in simulnk 

 

What if I buy a low-f oscillator as clock signal, does FPGA need a minimum frequency requirement for clock signal ?
Altera_Forum
Honored Contributor II
98 Views

If you are using dsp builder then please remember that the preferred way is using the primitives (if available, e.g., counter, etc.) first... rather than putting own code...  

 

About such a low frequency clock you first need to know that what is the default base clock in your design and how to change it.. Of course it has limits (both highest and lowest possible)... using 'Clock' block from "Altera DSP builder block set"... then further lower it down using a counter.... 

 

Hope it works...
Altera_Forum
Honored Contributor II
98 Views

In DSP Builder, you can try Clock/Clock_Derived to generate different clock, or you can try Tsamp to change clock...

Reply