questions about pcie hip and dma qsys design example

[Altera_Forum]

Hi all, 

 I have two questions about the "readaddress" and "writeaddress" registers of dma ip in PCIE Qsys design example. (the design example in PCIE user guide chapter 17) If I want the dma to copy some data from on-chip memory to an allocated memory in PC, what should I assign address to these two registers?   Because the on-chip memory is on the address of 0x0020_0000, I guess the value in "readaddress" register should be 0x0020_0000.  What value should I assign to the "writeaddress" register?  The second question is about 64-bit address. Since the "readaddress" and "writeaddress" registers are only 32-bit width, is it possible to use this dma ip to copy data from the on-chip memory to a x64 PC?  Thanks for any suggestion and reply.

[Altera_Forum]

After I study some posts in this forum and the "PCIE-to-AvalonMM address translation table" in PCIE user guide, I find the answers. 

 Today I start to write a program with Jungo driver in order to test the DMA. Now I have a new problem - the DMA status is always "busy" if I want to copy data more than 4 bytes from FPGA to PC. If I set the DMA length register as 4, DMA completes and I can see 4-bytes data. However, if I try to copy more data (8 bytes or 4096 bytes...), the DMA status register always shows me "busy" and the data in the allocated memories on PC are not changed.  Could anyone please give me some ideas on how the solve this problem? Thanks.