Hi All,
Hope you can help with these questions.
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Q1: A small NIOS system has been built with SOPC using SD_card interface (from university program), SDRAM, and some on-board SRAM.
The basic requirement is to load a file from SD card into SDRAM in a hurry. Current technique uses memcpy to move data between the SD card buffer and SDRAM which works fine, albeit slower than desirable.
Adding a memory mapped DMA controller (non SG), blocks of SDRAM can be moved around without any issue.
However, attempting to DMA between the SD_card buffer and SDRAM results in the first 4 bytes of SD_card buffer being copied repeatedly to SDRAM.
DMA controllers with and without burst mode have been tried - same results.
'end transaction when the length register reaches zero' mode is used for these tests.
Any thoughts about what might be going wrong here ?
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Q2; The GO bit (DMA control register B3) is used to initiate a DMA transfer, then writing '1' to the DONE bit (DMA status register B0) when transfer is complete. Rather expected the DMA controller to clear the GO bit when transfer has completed. Presumably the GO bit is edge sensitive (0 -> 1 transition starts the process). Any insight ?
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Q3: When using RCON mode, data is fetched from a constant address. How does the DMA controller know when data is available (in the case of a FIFO) ?
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Thanks,
Mark
