FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6424 Discussions

"Out of Frequency" on Monitor LCD

Honored Contributor II

Hi guys, 


I am building a simple Qsys example on a DE2-115 board. The Qsys only has a video test pattern generator and a clocked video output. Both the TPG and the CVO are configured to be 800x600 RGB format. The output of CVO is directly connected to the VGA port of DE2-115. Everything is clocked at 40 MHz, since the data is (800+256)x(600+28)x60Hz = 40MHz. The program compiled fine. But when I connected a external LCD monitor to it, the monitor only displayed "Out of frequency". I tried 33MHz and 25MHz as well, but the result is the same. Any suggestion? Thanks very much! 


The code between Qsys and VGA is as follows, where clk0 is at 40MHz: 


wire [23:0] wire_VGA_DATA; 

assign VGA_R = wire_VGA_DATA[23:16]; 

assign VGA_G = wire_VGA_DATA[15:8]; 

assign VGA_B = wire_VGA_DATA[7:0]; 

assign VGA_SYNC_N = 1'b0; 

assign VGA_CLK = clk0; 


DE2_115_SOPC DE2_115_SOPC_u0 ( 

//clock in 

.clk_clk (clk0), 

//reset in 

.reset_reset_n (1'b1), 


.video_out_vid_data (wire_VGA_DATA), 

.video_out_vid_datavalid (VGA_BLANK_N), 

.video_out_vid_h_sync (~VGA_HS), 

.video_out_vid_v_sync (~VGA_VS) 

0 Kudos
1 Reply
Honored Contributor II

Try connecting to a good multisync CRT - they may be more tolerant. 

Or put a 'scope onto the signals to check the hsync and vsync (and porches) look about right.
0 Kudos