regarding PARAMETER

[Altera_Forum]

Hi All, 

    is there any possibility to use parameter selecation in place of `ifdef and `else    Your timely response is very appreciated!   Regards Divyesh

[Altera_Forum]

If you really want a timely response, you'll have to give more details. What language are you using, what parameters are you talking about and what do you want to do with them?

[Altera_Forum]

ok i apologies for that. 

 i am using verilog.   my problem is that i want to instantiate one module more than one time using keyword perameter instead of ifdef. e.g.   `define EP1_ENABLE 1 `define EP2_ENABLE 1 . . . module test(); . . . . . // instance of other module  `ifdef EP1_ENABLE  ep_register   `else  ep_register_dummy   `endif   `ifdef EP2_ENABLE  ep_register u2(   .(),  );    `else ep_register_dummy u2(   .(),  ); `endif  endmodule  this implementations is using ifdef, we want same implementations using PARAMETER so please let me know if there is any way

[Altera_Forum]

You may want to consult your favourite Verilog text book or reference manual for the purpose of generate statement.

[Altera_Forum]

thanks for reply... 

 i got the solution for my problem.  In that as per perameter selection value implemented on hardware.  thanks again