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Altera_Forum
Honored Contributor I
755 Views

sdi IP core bug?

Hi,evrybody, I use EP3C5E144,use SDI core RX only,that mean it recieve the SDI and convernt to parallel signals,but the rx_clk is always keep "1",I think it should 27M clock,or not?Can you help me?

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3 Replies
Altera_Forum
Honored Contributor I
42 Views

I doubt the core changed from Quartus 10.1sp1, so it should work fine - I've tested the core. What clocks do You supply for the core? Afaik there's no 27MHz output, only 135MHz, so You need to supply 337,5MHz, 337,5MHz + 90deg and 135MHz clocks. It'll have valid pin every 5 clock periods.

Altera_Forum
Honored Contributor I
42 Views

why output is 135,but not 27?the parallel data is 27M,why clock is not the same

Altera_Forum
Honored Contributor I
42 Views

ask altera why did they make such clock output. Anyway, I had no problems using 135MHz output.

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