FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

signal compiler error

Honored Contributor II

i have done doing my simulink using DSP builder. 

but when to compile the simulink the error shows like this : 


Matlab Error 

Error using ==> alt_dspbuilder_mdl2xml at 29 

Error due to multiple causes. 

Error: Error during compilation: Error: Error analyzing model see log for details. 


what does it mean? anyone can help :confused: 


I'm using quarters 8.1 (free version), signal builder 8.0, and matlab 2009b.
0 Kudos
1 Reply
Honored Contributor II

I had similar problems, I think that you probably don't have an HDL file that one of your blocks is referencing in the same folder as your model. Mine was a problem with the pll_clock block being used by the HSMC card. If you started with one of the Altera examples but saved it in a different folder then you also need to move the clock files ( I think there was 6 actual files) to the same folder.

0 Kudos