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Multi frequency design in DSP Builder how manage clocks

Altera_Forum
Honored Contributor II
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i have a 64 bit divider in a design. i can't meet setup constraint @100MHz. 

 

i would then add a PLL that thake the 100 MHz base clock and outputs 

 

PLL_clk0 @ 100MHz for my design 

PLL_clk1 @ 50 MHz for the divider 

 

So i wuold use the Tsamp blocks outputting PLL_clk0 for all inputs and outputs at the boundaries of my dsp builder design 

 

and Tsamp blocks outputting PLL_clk1 at the input of my divider. 

 

Am i right? Or i should use the base clock and the PLL_clk1 only?
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Altera_Forum
Honored Contributor II
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If your are only failing to meet the setup constraints - then just delay the data until the next clock. 

If you are trying to do a 64bit divide in even 20ns you are being very hopeful! 

 

The simplest didvide logic will take approx 32 clocks (for 32bit divosor/quotent.
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Altera_Forum
Honored Contributor II
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thank you for your reply. 

I have 64 bit divider and divisor. 

I added 64 pipeline registers inside the divider. 

But i can't meet constraint at 100 MHz too. 

Now running at 50 MHz, setup constraints are met. 

 

I would like to know if i'm right with this solution or if a better solution is suggested and if i managed well the PLL in the design
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Altera_Forum
Honored Contributor II
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So you have 64 (ish) separate subtract-mux blocks separated by latches? 

Rather than a logic loop? 

Allowing you to feed in a new value every clock. 

 

You should be able to make the whole thing run at half speed by using an extra enable line for all the latches. 

 

There are much faster ways of doing divide that use a lot less logic.
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Altera_Forum
Honored Contributor II
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maybe there is a misunderstanding. 

i am using the divider of the standard blockset of Altera. 

In the GUI, i specified 64 stages of latency. 

i don't know how the divider works internally. 

 

I would know if i can use this divider at half frequency (50 MHz) and 64 stages of latency 

 

or if i have to do my own divider
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