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Altera_Forum
Honored Contributor I
1,522 Views

signed to unsigned

i, i want to convert a 10 bit signed into a 8 bit unsigned. i tried with the altbus, but when implemented if i input -32 i get FF instead of 0.  

Is there an other block? which settings i have to make?
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7 Replies
Altera_Forum
Honored Contributor I
38 Views

 

--- Quote Start ---  

i, i want to convert a 10 bit signed into a 8 bit unsigned. i tried with the altbus, but when implemented if i input -32 i get FF instead of 0.  

Is there an other block? which settings i have to make? 

--- Quote End ---  

What is the 10-bit signal representing? What do you want to have happen to the negative values in the signed input? 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
38 Views

This is the description of the AltBus block function: 

 

 

--- Quote Start ---  

The AltBus block modifies the bus format of a DSP Builder signal. Only use this block as an internal node in a system, not as an input to or output from the system. If the specified bit width is wider than the input bit width, the bus is sign extended to fit. If it is smaller than the input bit width, you can specify to either truncate or saturate the excess bits. 

--- Quote End ---  

 

 

In your case the following will happen 

 

input to AltBus: 

-32 (10 bit signed decimal) = 11 1110 0000 (binary) = 0x3E0 (hexadecimal) 

 

after AltBus with reduction to 8 bit unsigned: 

224 (8 bit unsigned) = 1110 000 (binary) = 0xE0 (hexadecimal) 

 

 

I think for your problem you need to check if your input is negative and set the output in this case to 0. 

Additionally check if a positive input is bigger then (2^8 - 1 = 255). Depending on your application saturate or truncate the MSB in this case.
Altera_Forum
Honored Contributor I
38 Views

thanks for your answer. when the input is negative i want 0 

if i set the alt bus unsigned 10 bit to 8, i get in simulation: 

 

-32 -> 0 

 

the problem is in the implementation where i get FF. 

 

So i used the Saturate block, 

 

i set the bus SIGNED, i took 9 bit in output rather than 8 and i set the limit for saturation 0 to 255. 

 

This works in implementation too.
Altera_Forum
Honored Contributor I
38 Views

Ok, I checked my simulation again and could reproduce your results after enabling the saturation in the Altbus block. And you are right the simulation produces '0' as output but already a VHDL simulation showed 255 (decimal) or 0xFF (hex). What is a result I would expect. 

 

To explain this here what happens: 

 

input to AltBus: 

-32 (10 bit signed decimal) = 11 1110 0000 (binary) = 0x3E0 (hexadecimal) 

 

convert to unsigned 

992 (10 bit unsigned decimal) = 11 1110 0000 (binary) = 0x3E0 (hexadecimal) 

 

saturate, then 992 > 255: 

255 (8 bit unsigned decimal) = 1111 1111 (binary) = 0xFF (hexadecimal)
Altera_Forum
Honored Contributor I
38 Views

thank you schmalish for your support. 

I think that a tool where implementation differs from simulink simulation is a bad tool. 

In Xylinx System Generator this type of thing doesn't happen! 

I spent a lot of time for this matter. 

 

Anyway how do you simulate VHDL?
Altera_Forum
Honored Contributor I
38 Views

I would suggest to open a Service Request for this issue. This way Altera can fix the Simulink simulation in a later version. 

 

To simulate VHDL just add the Testbench block to your model and open it. There you can start a VHDL simulation in ModelSim to compare the results to the Simulink simulation. 

 

By the way, I also had to discover lately the hard way a difference between the Simulink simulation and the real FPGA behavior. If you ever use a dualport RAM with MLAB's and you read from and write to the same address be prepared for a surprise. The Simulink simulation does a read before write behavior but the generated VHDL code does a write before read.
Altera_Forum
Honored Contributor I
38 Views

thank you i'm very disappointed with this tool. 

Ever if i met constraints my design don't properly worked. 

I needed to add some other constraint (multicycle on a downsampled data) to correctly interface my dsp builder design with the rest of the SOPC design.
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