A beginner with FPGA design - I am using the Transceiver BoardCyclone IV GX EP4CGX15BF14 - The speed grade of the device is capable of 2.5Gbps. I spent days reading through the tutorials, training and manuals...Ughhh I want to design a cyclic serializer that will repeat an address selectable sequence of 128bits at the maximum bit rate. (no protocol, erc or handshake bits are to be used). Using the MegaWizard I instantiated an ALTLVDS_TX component with 8bit in, one channel out, Data rate 2500 (Mbps) PLL_lock signal and Byte_clock=2500/8=312.5MBps 1. I am uncertain that the core of the FPGA can support the 312.5MBps data rate - I read that some FPGA's can have double byte input to halve the input data rate - however I did not find an appropriate option like that in the MegaWizard. Any ideas how to interface the input of the serializer to memory (clearly I need to cycle through 16 addresses for an 8bit wide memory for each 128bit long sequence)? 2. I am not sure that I selected the correct signal types for a component in Qsys - see attached Qsys file - the data input to the serializer specifically I used Avalon Streaming slave. 3. I defined the reference clock for the Serializer data input using the Byte_clock and I need to create an addressing scheme and a pipeline? so that a new byte is available at the dataInput of the serializer after it serializes the current byte? I would appreciate any suggestions
Here is Altera's responses on the subject:The double-width modes or single-width modes are meant for the transceivers, which is used in the ALTGX megafunctions. However, for ALTLVDS the serialization factor is limited until 10. Means if you would need 2 bit on the output, and each driving 8 bit data input which gives 16:2. It is impossible to have 16:1 from the meagfunction either in soft or hard serdes. The only way would be to pay some effort for writing own code for the serdes ALTLVDS_TX can not support 2.5Gbps data rate on Cyclone IV GX device family, you might want to use ALTGX instead.