We are VLSI design center and we made several designs before, using FPGAs, by writing the required codes and testbench for functional and timing simulation of the design, then download the design on the hardware . Currently we have a design that uses IPs only . We implemented it using SOPC builder and we have also a development board for hardware testing .
My question is : do we need to write the testbench for this design in order to perform functional simulation first then download it on the development board ? or can we skip the functional simulation since the design consists of IPs only and these IPs are tested by Altera?
