Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
929 Views

the Transceiver IPcore in Stratix IV GX can't work well

hello, 

The transceiver can't locked the input port of pll_inclk,when i use the IPcore . the output port of pll_locked always be low. and the tx_dataout can't output at the correct rate. 

 

PS: pll_inclk not form the refclk0 and refclk1 pins of the same transceiver block ,but the left and right PLLs in the FPGA fabric . 

 

for example:set clock rate at 50M and data rate at 1600M in Mega Wizard Plug—In Manager, but the output data rate of tx_dataout is only 800M ,and the pll_locked always be low 

 

 

Thanks 

 

Best Regards 

 

flzhn
0 Kudos
7 Replies
Altera_Forum
Honored Contributor I
34 Views

no one knows?give me a hand,if anyone can help me Thanks

Altera_Forum
Honored Contributor I
34 Views

It works fine for me. 

 

Why don't you explain what you have tried so far. 

 

1) What are you trying to use the transceivers for? 

 

2) How have you setup the IP core? Basic single/double-width mode, lane rates, number of channels, transmitter/receiver, etc. 

 

3) Have you connected an ALTGX_RECONFIG block to it and are you clocking it correctly? 

 

4) Have you created a reset controller that resets the ALTGX component according to the mode you are using it? 

 

5) Have you written a Modelsim simulation to show that your design works in simulation? 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
34 Views

thanks Dave 

 

1. i use the transceivers just to transmit the data in FPGA . 

2. i setup the transceivers as described below: 

a> Basic double-width mode 

b> only 1 channel 

c> operation mode is Transmitter only 

d> channel width is 40 bits 

e> input clk frequency is 200 MHz and lane rate is 4Gbps 

f> Tx PLL bandwidth mode is Medium 

 

other option is default 

3. only have a Transmitter,so there is no ALTGX_RECONFIG block in the project 

4. i have designed a reset controller to resets the ALTGX, just as described in “Transceiver Reset Sequences” of《Reset Control and Power Down in Stratix IV Devices》 

5.i have finished the simulation in Modelsim SE 6.1,everything is all right,so it's confused me. 

 

ps: I Programming the same .sof in Stratix IV GX for many times.But the result is different ,sometimes the tx_clkout is right, sometimes tx_clkout is wrong,and the pll_locked is invalid.  

in my opinion,it may be the problem of CMU,but i don't know how to change the project to let it be well.  

 

by the way,if necessary ,i can Email my project to you . 

 

thanks very much 

best regards  

 

flzhn
Altera_Forum
Honored Contributor I
34 Views

 

--- Quote Start ---  

 

1. i use the transceivers just to transmit the data in FPGA . 

2. i setup the transceivers as described below: 

a> Basic double-width mode 

b> only 1 channel 

c> operation mode is Transmitter only 

d> channel width is 40 bits 

e> input clk frequency is 200 MHz and lane rate is 4Gbps 

f> Tx PLL bandwidth mode is Medium 

 

other option is default 

3. only have a Transmitter,so there is no ALTGX_RECONFIG block in the project 

4. i have designed a reset controller to resets the ALTGX, just as described in “Transceiver Reset Sequences” of《Reset Control and Power Down in Stratix IV Devices》 

5.i have finished the simulation in Modelsim SE 6.1,everything is all right,so it's confused me. 

 

--- Quote End ---  

It sounds like you have configured everything correctly. 

 

Have you tried different data rates and clock sources to see if you get a different result? You can use a global clock to generate a PLL output that can then be used as the transmitter reference clock. For the purpose of debugging, this should be fine. It does work, as I have tried it on the Stratix IV GX development kit to change the 100MHz reference into a 156.25MHz reference. 

 

 

--- Quote Start ---  

 

I Programming the same .sof in Stratix IV GX for many times.But the result is different ,sometimes the tx_clkout is right, sometimes tx_clkout is wrong,and the pll_locked is invalid.  

in my opinion,it may be the problem of CMU,but i don't know how to change the project to let it be well.  

 

--- Quote End ---  

Are you sure your 200MHz reference clock is good? What about power supplies? Is this a custom board? Do you have an Altera reference board you can compare to. 

 

Have you used SignalTap II to generate a trace of what happens near the time the PLL comes unlocked? For example, set a trigger on your reset controller at the end of the reset sequence, and ensure that all the timing looks like that in the handbook. Then, set another trigger for when the PLL unlocks. Perhaps the traces of the other control signals will tell you what could be wrong. 

 

 

--- Quote Start ---  

 

by the way, if necessary, i can Email my project to you. 

 

--- Quote End ---  

Lets see how we go, and then if we cannot find a solution, I can try your design on the Stratix IV GX development kit to see if it works. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
34 Views

thanks Dave 

 

yes,i have tried different data rate,1.6Gbps,2Gbps,4Gbps,5Gbps,8Gbps...sometimes it's all work well,but the result is not correct for most of times. 

 

for the reference clock,i'm sure it's good. i use Oscilloscope to test the clock,and it's displays well. 

 

the board is not custom board,it's made by ourselves,and we don't have any Altera reference board to compare .May be it's the problem of the board,but the pin Pins are connected correctly,and power supplies well. 

 

i will try the way of SignalTap II to test if all the control signal is right. 

 

i hope there is something wrong in my logic,but not the board.god bless... 

 

thanks for your advice 

 

best regards 

 

flzhn
Altera_Forum
Honored Contributor I
34 Views

 

--- Quote Start ---  

 

yes,i have tried different data rate,1.6Gbps,2Gbps,4Gbps,5Gbps,8Gbps...sometimes it's all work well,but the result is not correct for most of times. 

 

--- Quote End ---  

How do you determine that the data is not correct? You said you were only configuring the transceiver as a transmitter. I assume that means the receiver is being used to determine that things are bad. How do you know it is not the receiver that is bad? 

 

Can you loop the transmitter back to a receiver channel? Actually, there is an internal loopback too, have you tested that? 

 

Do you AC-couple to your receiver, or DC-couple? Perhaps you are stressing the transmitter drivers. 

 

 

--- Quote Start ---  

 

for the reference clock,i'm sure it's good. i use Oscilloscope to test the clock,and it's displays well. 

 

--- Quote End ---  

Ok. 

 

 

--- Quote Start ---  

 

the board is not custom board,it's made by ourselves,and we don't have any Altera reference board to compare .May be it's the problem of the board,but the pin Pins are connected correctly,and power supplies well. 

 

--- Quote End ---  

Do you have more than one of these boards? Do they all behave the same? 

 

 

--- Quote Start ---  

 

i will try the way of SignalTap II to test if all the control signal is right. 

 

--- Quote End ---  

Its a very useful tool. 

 

 

--- Quote Start ---  

 

i hope there is something wrong in my logic, but not the board. 

 

--- Quote End ---  

Good luck! 

 

Cheers, 

Dave
Glen
Beginner
34 Views

Hi,

Have you resolved this issue?

We just meet a similiar problem on stratix iv device. ALTGX is configured as transmitter only mode, but the CMU PLL is unlocked.

Best regards,

glen