We are using EMIF IP for Agilex FPGA in our design. Rather than using automatic refreshes, we use user controlled refreshes through mmr interface.
Please can you help me figure out if read/write commands are not accepted by the IP when we issue user refresh?
user guide i am refering to is:
External Memory Interfaces Intel®
Agilex™ FPGA IP User Guide
Updated for Intel® Quartus® Prime Design Suite: 21.4
IP Version: 2.6.0
Is there a way to prioritize read/write commands over user refresh?
I would like to simulate this using example design but current example design does not have user control refresh logic.
do you have any other example design which can help me understand user refresh and read/write command interaction?
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