user issued emif refresh and read/write commands

[CosmoKramer]

We are using EMIF IP for Agilex FPGA in our design. Rather than using automatic refreshes, we use user controlled refreshes through mmr interface. 

Please can you help me figure out if read/write commands are not accepted by the IP when we issue user refresh?

user guide i am refering to is:

External Memory Interfaces Intel®
Agilex™ FPGA IP User Guide
Updated for Intel® Quartus® Prime Design Suite: 21.4
IP Version: 2.6.0

Regards, 

Sandy

[AdzimZM_Intel]

Hi Sandy,

The read/write commands will be interrupted when performing user refresh.

Regards,

Adzim

[CosmoKramer]

Is there a way to prioritize read/write commands over user refresh?

I would like to simulate this using example design but current example design does not have user control refresh logic. 

do you have any other example design which can help me understand user refresh and read/write command interaction?

[AdzimZM_Intel]

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.