02-04-2013 09:08 AM
Hello.I have builded very simple test design with DSP builder advanced blockset (ModelPrim blocks only) for calculating angle from accelerometer data. It has channel in/out, two convert blocks and one trig block (atan function). I don't use folding. The system is running at 30MHz and data sample rate is 0.0008MHz (800Hz). I am driving valid in signal at 800hz frequency (valid in is '1' for one period of 30MHz clock every 30/0.0008 clock cycle). This design works perfect - here timing diagram from signalTap. Data_y and data_z are data from accelerometer (int16), dout and vout are data out and valid out fom DSB BUilder subsystem. As you can notice, dout is constant after it has changed and valid out looks fine. https://www.alteraforum.com/forum/attachment.php?attachmentid=6754 Than I have added integration and differentiation block (I want to verificate these blocks). And again it has worked fine, I get angle. https://www.alteraforum.com/forum/attachment.php?attachmentid=6755 Then I have deleted integration block, because I want to get angle velocity. And it didn't work, I got zero. I looked at timing diagrams and found something strange: dout is non-zero only when vout is '1'. Other time it is zero. It is strange, because in last two timing diagrams dout is constant between transactions.https://www.alteraforum.com/forum/attachment.php?attachmentid=6756 I don't understand such difference in those three timing diagrams and why system with atan and differentiator give me zero. Thank you. Here are three designs attached.
02-04-2013 06:56 PM
Your problem is far from clear.your signal valid_o seems to have two rates. two clocks in first or second signaltap but one clock in third signaltap. Is that expected. vout has one clock duration then becomes two clocks??
02-04-2013 07:29 PM
--- Quote Start --- My block is clocked by 30MHz but signaltap is clocked by 50MHz. Change my block clocking, but forget to change signaltap's reference clock. --- Quote End --- For reliable signaltap reading you should use same clock that samples the data in your logic otherwise you get signaltap timing or phase issues.