FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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6154 Discussions

connection between VIP suite and SGDMA (inconsistent data width)

Honored Contributor II

Hi all 


My project is to transfer video data to PCIE. 


As my first step, I try to use Test Pattern Generator (TPG) as a temporary video data input and connect the output data from TPG to SGDMA via the Avalon Streaming Interface. The SGDMA works in the transfer mode of "stream-to-memory" and its output is connected to a SDRAM controller IP. 


My problem is the inconsistent data width between TPG output and SGDMA input. 

The parameter settings in TPG are 720-by-480, 10-bits, and YCbCr 4:2:2. (I'm going to use SDI receiver as the interface of real video data input so the data width must be 10-bits) 

QSys shows an error message "Error: System.tpg.dout/sgdma_0.in: The source has 10 bits per symbol, while the sink has 8." 


Does anyone know how to solve this problem? 

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2 Replies
Honored Contributor II

How did You solve this problem?

Honored Contributor II

Make your source video from the TPG be 8 bits. 

When you output to your SDI receiver, connect the 8 bit video from the TPG to the 8 MSBs of the 10 bit SDI interface. 

The low 2 LSBs you can just set to zero. 


like so: 


SDI_video(9 downto 2) <= TPG_vid_out; 

SDI_video(1 downto 0) <= "00";