FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6422 Discussions

vid_hsync and vid_vsync timing specifications.

TPH_zenith
Novice
734 Views

What are the timing specifications for vid_hsync and vid_vsync inputs for the Intel HDMI IP ver. 19.6.0 when used as an HDMI source. These signals are shown on page 74 of the UG-HDMI 2020-12-14

0 Kudos
2 Replies
BoonT_Intel
Moderator
706 Views

Hi Sir,

For the hsync and vsync timing diagram, you may refer to figure 4, 5, 6 and 7 in page 10.

If you want to check the timing in details, you may setup the example design simulation and check how the design sending the hsync and vsync data.



0 Kudos
BoonT_Intel
Moderator
682 Views

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


0 Kudos
Reply