FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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what are the parameter settings for enabling the SPI-4.2 POS PHY IP core

Honored Contributor II


i am trying to enable the SPI-4.2 POS PHY IP core in the RTM interface card. I am trying to achieve a data rate of 200 Mbps and with 32-bit data path width variation. i am facing problems like 

1. dip4 error is toggling when i am receiving data but no errors while receiving training sequence  

2. stat_rd_rdat_sync also toggling while receiving data 


can you please suggest me the working parameter settings for both the transmitter and receiver ??
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