what are the parameter settings for enabling the SPI-4.2 POS PHY IP core

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

what are the parameter settings for enabling the SPI-4.2 POS PHY IP core

799 Views

i am trying to enable the SPI-4.2 POS PHY IP core in the RTM interface card. I am trying to achieve a data rate of 200 Mbps and with 32-bit data path width variation. i am facing problems like

1. dip4 error is toggling when i am receiving data but no errors while receiving training sequence

2. stat_rd_rdat_sync also toggling while receiving data

can you please suggest me the working parameter settings for both the transmitter and receiver ??

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.