Hi,I am new to DSP builder and FPGA programming. I was following DSP builder example which was on implementing FIR filter using DSP builder in Simulink and generating VHDL to be implement in my cyclone 2 FPGA. I came across this block as was given in the example steps which was "HDL SubSystem block" but I can't seem to find this block in my DSP builder library... could someone tell me what is wrong... I even tried reinstalling DSP builder..
I'm not familiar with this example, could you link the document and the page number? (It's likely that an ordinary simulink subsystem is what you need. I think DSP Builder prior to 7.0 required special subsystems for hierarchy, but that went away with 7.1).
Hi dabuk, the document I am using to design my FIR filter is in a hardcopy, I will post the page sometime later but here is the link from DSP builder manual which also has an example which uses HDL SubSystem.... it on page 83...http://www.europractice.stfc.ac.uk/vendors/ug_dsp_builder.pdf
That document is very old.http://www.altera.com/literature/hb/dspb/hb_dspb_std.pdf (http://www.altera.com/literature/hb/dspb/hb_dspb_std.pdf) is much more up-to-date. Chapter 9 there seems to describe the same sort of thing but it should actually work.
Hi dabukhere is the tutorial that I have been using to design me FIR filter using simulink.... its on page 39 step 10 from adobe file....its on the 2nd section Implementing DSP design using FPGA.... http://www.4shared.com/document/aa54ymng/scandoc__3_.html thanks
The date on that document is 2004. DSP Builder 7.1 changed many things and was released in 2007. Unless you are using DSP Builder 7.0 or earlier, that document is very unlikely to be a useful source of information.
All I want to do is to design FIR filter in simulink.... and I dont seem to find any document that shows steps on desiging FIR filter on simulink like the one mention in this document....could you help me find such document....