FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5954 Discussions

why atx pll output clock should be half of data rate?

AGonn
Beginner
842 Views
 
0 Kudos
1 Reply
Abe
Valued Contributor II
106 Views

When using serial protocols such as Serdes / PCIe, etc, the output data rate is achieved by using both edges of the clock. This is called Double-Data Rate (DDR) . In this scenario , to achieve the high data rate we only need to use the clock with half of the data rate. When the data is output at both edges (rising and falling) of the half rate clock, you will get the full data rate of the protocol.

Reply