在C10GX中的DDR3 IP avalon 位宽如何修改？

[TGao]

Hi 您好，

在C10GX中的DDR3 IP 设置中avalon 位宽如何修改？

Ted​

[NurAida_A_Intel]

Dear Ted,

Thank you for joining this Intel Community.

Unfortunately, there is no other option as the avalon width is depend on the controller (I believed in your case is DDR3L) data width. You need to either increase or decrease your DDR3L data width in order to have your required avalon input data width.

I am so sorry for the inconvenience caused.

Thanks

Regards,

Aida

[TGao]

Hi Aida，

Thanks for your reply.

Yes, It;s DDR3L. and Maybe I describe not clearly, the width I mean is "Maxmun avalon-mm burst length" . This is easily changed in lpddr2 but I can't find in DDR3L .

Ted​

[NurAida_A_Intel]

Hello Ted,

May I know which Quartus version are you using?

Regards,

Aida

[TGao]

HI Aida,

Quartus 18.1 Pro. Thanks

Ted

[NurAida_A_Intel · Accepted solution]

Hi Ted,

Thank you for the Quartus version confirmation.

The parameter is actually hidden in the Quartus. Under the "Controller" tab, you need to right click the EMIF GUI and click "Show Hidden Parameter" as shown below

Then just scroll down and you will be able to see the "Maximum avalon-mm burst length" setting as per highlighted in yellow.

Kindly let me know if you still unable to see it.

Thanks

Regards,

Aida

[TGao]

Hi Aida，

It's Great， Thanks for your Help！

Ted​