FPGA, SoC, And CPLD Boards And Kits
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ADC Cyclone III Dev. Kit

Altera_Forum
Honored Contributor II
‎09-23-2010 02:02 PM
1,228 Views

I'm using the ADC Port A on the HSMC Mezzanine Card. The ADC is the AD9254. I want to control the sample rate. After reading the data sheet I'm still not sure how this is possible. 

It says the CLK+ and CLK- are the clock input signals for the AD9254 and that sample rates can varie between 10 and 150 MSPS. There is a data output clock, the DCO, which determines the speed in which the data comes out of the chip. Can I change the speed of the DCO? What is the speed of the DCO? 

 

thx!
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Altera_Forum
Honored Contributor II
‎09-27-2010 07:47 AM
515 Views

have the same problem too. i'm new user of fpga. and using vhdl codes. i can use dac block but it's output range between -220 mV and 448mV is it normal ? and how can i send dac outputs to adc's input, or have can i programme dsp builder's adc converter?

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