FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

ADC Cyclone III Dev. Kit

Altera_Forum
Honored Contributor II
811 Views

I'm using the ADC Port A on the HSMC Mezzanine Card. The ADC is the AD9254. I want to control the sample rate. After reading the data sheet I'm still not sure how this is possible. 

It says the CLK+ and CLK- are the clock input signals for the AD9254 and that sample rates can varie between 10 and 150 MSPS. There is a data output clock, the DCO, which determines the speed in which the data comes out of the chip. Can I change the speed of the DCO? What is the speed of the DCO? 

 

thx!
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
98 Views

have the same problem too. i'm new user of fpga. and using vhdl codes. i can use dac block but it's output range between -220 mV and 448mV is it normal ? and how can i send dac outputs to adc's input, or have can i programme dsp builder's adc converter?

Reply