AXI Streaming Intel FPGA IP for PCI Express design example failing simulation

[Nick_kb]

Hello,

An example design was generated using the AXI Streaming Intel FPGA IP for PCI Express in Quartus Prime Pro Edition 2025.1.

The configuration was left mostly at default, with the following key settings:

• Target device: Intel Agilex 7, part number AGFB014R24C2E2V
• PCIe configuration: Gen4 x16, Native Endpoint
• Example design option: PERFORMANCE_DESIGN

Simulations with Questa FE and Riviera Pro are both failing.

For Questa FE

Simulation with Questa Intel FPGA Edition-64 2024.3 shows many errors related to unresolved references then ends with a .tcl pause as seen in last few lines of the log below

# ** Error: (vsim-3043) Unresolved reference to 'o_txpipe9__txstartblock' in z1577b_x5_y0_n0.z1577b.z1577b_inst.o_txpipe9__txstartblock.
# Time: 0 fs Iteration: 0 Instance: /pcie_ss_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ss_ed_sim_auto_tiles.sv Line: 44447
# ** Warning: (vsim-3008) [CNNODP] - Component name (o_txpipe9__txswing) is not on a downward path.
# Time: 0 fs Iteration: 0 Instance: /pcie_ss_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ss_ed_sim_auto_tiles.sv Line: 44447
# ** Error: (vsim-3043) Unresolved reference to 'o_txpipe9__txswing' in z1577b_x5_y0_n0.z1577b.z1577b_inst.o_txpipe9__txswing.
# Time: 0 fs Iteration: 0 Instance: /pcie_ss_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ss_ed_sim_auto_tiles.sv Line: 44447
# ** Warning: (vsim-3008) [CNNODP] - Component name (o_txpipe9__txsyncheader) is not on a downward path.
# Time: 0 fs Iteration: 0 Instance: /pcie_ss_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ss_ed_sim_auto_tiles.sv Line: 44447
# ** Error: (vsim-3043) Unresolved reference to 'o_txpipe9__txsyncheader' in z1577b_x5_y0_n0.z1577b.z1577b_inst.o_txpipe9__txsyncheader.
# Time: 0 fs Iteration: 0 Instance: /pcie_ss_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ss_ed_sim_auto_tiles.sv Line: 44447
# ** Warning: (vsim-3008) [CNNODP] - Component name (o_txpipe9__width) is not on a downward path.
# Time: 0 fs Iteration: 0 Instance: /pcie_ss_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ss_ed_sim_auto_tiles.sv Line: 44447
# ** Error: (vsim-3043) Unresolved reference to 'o_txpipe9__width' in z1577b_x5_y0_n0.z1577b.z1577b_inst.o_txpipe9__width.
# Time: 0 fs Iteration: 0 Instance: /pcie_ss_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ss_ed_sim_auto_tiles.sv Line: 44447
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./run_msim.tcl PAUSED at line 17

For Riviera Pro

The generated design was simulated using Riviera-PRO 2025.4, but the simulation failed very early due to the error VCP1252 as seen in log below:

# ALOG: Compile success 0 Errors 0 Warnings  Analysis time: 0[s].

# ALOG: done

# ALOG: Warning: VCP1251 /home/nick.kabawa/AxilexKit/25_1/f_tile_design_example/pcie_ss_ed_sim_tb/pcie_ss_ed_sim_tb/sim/aldec/intel_pcie_rtile_crdt_tx_slice.sv : (87, 7): The warning message cannot be shown because a protected code block was seen in the current compilation session. Any further warnings will be disregarded.

# ALOG: Compile success 0 Errors 1 Warnings (1 protected)  Analysis time: 0[s].

# ALOG: done

# ALOG: Warning: VCP1251 /home/nick.kabawa/AxilexKit/25_1/f_tile_design_example/pcie_ss_ed_sim_tb/pcie_ss_ed_sim_tb/sim/aldec/tx_packer.sv : (653, 11): The warning message cannot be shown because a protected code block was seen in the current compilation session. Any further warnings will be disregarded.

# ALOG: Compile success 0 Errors 1 Warnings (1 protected)  Analysis time: 0[s].

# ALOG: done

# ALOG: Warning: VCP1251 /home/nick.kabawa/AxilexKit/25_1/f_tile_design_example/pcie_ss_ed_sim_tb/pcie_ss_ed_sim_tb/sim/aldec/pciess_tx_pudm_wrapper.sv : (199, 140): The warning message cannot be shown because a protected code block was seen in the current compilation session. Any further warnings will be disregarded.

# ALOG: Error: VCP1252 /home/nick.kabawa/AxilexKit/25_1/f_tile_design_example/pcie_ss_ed_sim_tb/pcie_ss_ed_sim_tb/sim/aldec/pciess_axist_2_avst_conv.sv : (146, 76): The error message cannot be shown because a protected code block was seen in the current compilation session.

# ALOG: Compile failure 1 Errors (1 protected) 1 Warnings (3 protected)  Analysis time: 0[s].

We attempted to force the compilation of the file pciess_axist_2_avst_conv.sv using IEEE SystemVerilog-2005 by modifying all related .tcl compilation lines to include the -sv2k5 flag. However, this had no effect, and the same error continued to appear.

Could you please provide some support to resolve this issue?

Note that
OS: Linux Ubuntu
Platform: Linux 64
Architecture: 64 bits

Kind regards

[ventt · Accepted solution]

Hi Nick_kb,

Thanks for reaching out.

According to the user guide, the SR-IOV and Performance design examples are not supported in this release. Ignore the selections for these design examples in the IP Parameter Editor. The current version of the AXI Streaming FPGA IP only supports the PIO design example. Therefore, please try the PIO design example.

Additionally, please note that you are using an F-tile device, but the AXI Streaming Intel FPGA IP for PCI Express currently supports only Agilex 7 devices with R-Tile. 

Regarding the simulator, please use the simulators supported on the PIO design example (VCS, VCSMX, Questasim, and Modelsim). In addition, the supported IP configurations are Gen5 1x16/2x8. For more details, please refer to Table 4 and Table 5.

Kindly refer to the user guide below.

AXI Streaming Intel® FPGA IP for PCI Express* User Guide (24.3.1 latest): https://www.intel.com/content/www/us/en/docs/programmable/790711/24-3-1/supported-features.html

Thanks.

Best Regards,

Ven

[Nick_kb]

Thank you for the clarification Ven.

I expected that since the project is set to a device with package R24C then Quartus knew this device has two F-Tiles and will only display compatible IPs to pick from. That's what made me think this IP supports F-Tile

[ventt]

Hi Nick_kb, 

I believe you are correct that Quartus only displays compatible IPs in the IP Catalog based on the selected device. 

I have observed that when the F-Tile device is selected in Quartus Prime Pro version 24.3.1, the AXI Streaming Intel FPGA IP for PCI Express is not available in the IP Catalog. However, it does appear in the IP Catalog when switching to Quartus version 25.1. I will share this feedback with the internal team.  

We should follow the supported devices as stated in the User Guide (24.3.1 latest), which is R-Tile in this case. 

Please let me know if you have any further inquiries on this forum.  

If there are no further inquiries, I will transition this thread to community support. 

Thanks. 

Best Regards, 

Ven 

[ventt]

Hi Nick_kb,

As there are no further inquiries, I will transition this thread to community support.  

Please log in to ‘https://supporttickets.intel.com’, view details of the desired request, and post a feed/response within the next 15 days to allow me to continue to support you. 

After 15 days, this thread will be transitioned to community support. 

Community users will be able to assist you with your follow-up questions. 

Thanks. 

Best Regards, 

Ven