Access DDR3 RAM from Linux program on HPS

[Sperber]

Hi,

I'm a newbie to SOC so I hope my question is not too stupid.

I'm using a Cyclone V SOC on a Terasic DE-10 Nano Board.

My goal is to receive data on the HPS side over Ethernet and to store this data into the DDR3 RAM Memory. The FPGA should modify this data later.

I'm running a C++ programm in linux on the HPS to receive the data by Ethernet, which works well.

Now I'm trying to store the data in the DDR3 RAM, but I have no idea how to do it so that I can address the data afterwards by the FPGA.

Are there special C++ commands to store data into the DDR3 RAM memory or is allocated memory automatically stored into the DDR3 RAM? If so, how can I address the data from the FPGA side again?

Maybe there is some kind of documentation or tutorial I missed until now.

Thank you very much.

Best regards

Johann

[EBERLAZARE_I_Intel]

Helo,

May I know which DDR3 RAM are you referring to? Is it on the HPS side or the FPGA side? 

Correct me if I am wrong, you want to receive data from Ethernet to HPS DDR3 or via HPS, then send the data to be stored in FPGA's memory?

[Sperber]

Hi Berlazare_I_Intel,

thank you for your answer.

I want to address the external DDR3 memory (1GB), build in in the Terasic DE10-nano Board.

In the user manual of this evaluation board it is written, that it is connected to the dedicated Hard Memory Controller for the HPS.

So I guess my question better should be: How can I work with the Hard memory controller of the HPS from a C++ application running on Linux on the ARM Processor.

My C++ application received data over ethernet which I want to store  in the external DDR memory of the DE10-nano board.

I don't want to use the FPGA fabric right now. The application is running on the linux distribution on the ARM processor of the HPS.

In the meantime I found an example how to write data into the DDR3 memory from Preloader on page 33 of the following document:

(https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_fd_controller_hps.pdf).

In this example data is just written to a memory space starting at the address 0x100000 .

long *base= 0x100000;

addr = base + cnt; /* pointer arith! */

sync ();

*addr = data_temp[i];

Is this what I need to do?

Do I have to map the memory somehow before I can use it?

Where is written that the base address is 0x100000 ?

I had a look into the Cyclone V HPS Memory Map (https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#topic/sfo1418687413697.html) but I didn't find the address 0x100000

Thank you very much.

Best regards

Johann

[EBERLAZARE_I_Intel]

Hi,

You may find the information in our Cyclone V SoC HPS TRM section here:

https://www.intel.com/content/www/us/en/programmable/documentation/sfo1410143707420.html#iga1415315895514

The address 0x1000000 is by default, MPU accesses to locations between 0x100000 (1 MB) to 0xC0000000 (3 GB) which is made to the SDRAM controller.