Agilex F-Series FPGA Dev Kit example design compilation

[veriguy]

It looks like the example design supplied with dev-kit "golden_top" has not actually been compiled. There is a typo in the verilog file that causes a syntax error during rtl analysis & synthesis phase. After fixing the typo, I was able to complete the analysis & synthesis phase. However now it looks like I/Os with 2 different voltage standards are assigned to HPS bank. When I compile I get the following error. Any suggestions on how to fix this problem?

Info(11929): '1.8V' is a valid VCCIO value
Info(11929): '1.2V' is a valid VCCIO value
Error(11924): Bank 'HPS' has conflicting VCCIO settings
Error(11928): 'hps_osc_clk~pad' with I/O standard 1.8 V, was constrained to be within bank 'HPS'
Info(11929): '1.8V' is a valid VCCIO value
Error(11928): 'emmc_clk~pad' with I/O standard 1.2 V, was constrained to be within bank 'HPS'
Info(11929): '1.2V' is a valid VCCIO value
Error(11928): 'hps_osc_clk~pad' with I/O standard 1.8 V, was constrained to be within bank 'HPS'
Info(11929): '1.8V' is a valid VCCIO value
Error(11928): 'emmc_clk~pad' with I/O standard 1.2 V, was constrained to be within bank 'HPS'
Info(11929): '1.2V' is a valid VCCIO value

[EngWei_O_Intel]

Hi there

Can you share the pin assignment that has been done on those pins? Perhaps is it possible for you to share the simple design that generating this?

Thanks.

Eng Wei

[veriguy]

Hi Eng Wei,

    Here I have attached a simple project based on the example design supplied in the dev-kit. I have modified the verilog file to include a simple counter to light up the LEDs in the sequence of numbers. The fitter does not complete due to the error above, so the pin file is not produced. However, the pin assignments are in qsf file. You can simply compile this project to reproduce the error. I used Quartus version 21.1 to compile this.

Thanks

Anshu

[EngWei_O_Intel]

Hi Anshu

I don't see the above mentioned errors in the compilation. 

The very 1st error I am seeing is as below:

Error(20732): I/O pin "fm6_pcie_perstn~CLUSTER" is a GPIO, but "BU58" has no GPIO resource. 

I believe it is due to the pin is not connected to any transceiver logic in the design. Removing assignment on this pin help the compilation to move forward, but hitting a lot of fitter issues due to most of the transceiver pins are not connected. Possible related to this:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd01022012_343.html

For the errors you mentioned in your initial thread,  most likely the IO standard you assigned on those pins are not compatible with the associated banks.

Thanks.

Eng Wei

[veriguy]

Hi Eng Wei,

    For some reason the archived project does show the above error. Taking a step back, I am trying to compile a project for Agilex F-series development kit. There are some example designs included, however am not able to successfully compile any of the few I tried,as they all ran into some kind of error or the other. Can you please direct me to an example design or project template that would have the pin assignments and other recommended settings and that I can use as starting point for my design? 

[veriguy]

The following link for the documentation for the kit points to the golden_top as the ref design. Even after removing the transciever pins I am not able to compile. Is there a clean example design for this kit that will compile as is? 

https://www.intel.com/content/www/us/en/programmable/documentation/zbg1567202330317.html#uqj1567213591882

[veriguy · Accepted solution]

Able to compile after removing the transceiver pins from top verilog file as well as qsf file. Missed a pin last time, that is why it was not compiling.

[EngWei_O_Intel]

Hi there

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Thanks.

Eng Wei