We are building Linux OS for our custom board , using reference design of Altera Arria 10 SoC.
In the HPS side, we have connected DDR3 whose clock is provided from Si5338 Clock Synthesizer IC. In order to boot the OS image , we need to enable the DDR3 . We are taking reference from https://rocketboards.org/foswiki/Documentation/ProgramSi5338QuadClockGeneratorOnArria10SoCDevKit
In this document it states that some register settings and a script file is required to generate output from this IC , but in order to run this script over board, first that board need to boot , which is only possible if DDR3 is enabled. So we are confused in this loop of clock generation.
If this clock is enabled in device tree , how the first stage of booting is happening?
Can someone please tell , how to enable the Si5338 IC to generate the clock for HPS DDR3 bank?
Welcome to INTEL forum. To control on board clock generator chip Si5338 you can refer link https://www.silabs.com/documents/public/data-sheets/Si5338.pdf
You could also check with Si5338 chip vendor directly if have further questions on how to use the chip https://www.silabs.com/about-us/contact-us