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Arria V GX with HSMC debug header pin assignments

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Hello,

 

I would like to get the Arria V DK-START-5AGXB3N starter board to communicate with another FPGA through I2C module that I've created (verilog), but I don't know how the GPIO pins are wired internally. The pin planner of Quartus software doesn't show which pins are which.

 

I've done this using Cyclone 10 before and I was lucky to find a board block diagram which maps the GPIO to the pin number of the FPGA chip. With the Arria V GX (5AGXFB3H4F35C5N), I could not find anything online or from the documentation kits.

 

The kit comes with HSMC debug header but I don't know if this can be used as GPIO and if so, how is it mapped to the FPGA pins?

 

Maybe I have missed something here, can somebody point me to the right direction?

 

Edit: I realized the pin connections to the FPGA are found in the schematic, but I still don't know which ones are available for users.

 

 

Thank you!

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Hello Done checking with team. For GPIO you can use LVDS or 2.5-V pin except the Transceiver pin. Refer link for HSMC Port A Pin Assignments, Schematic Signal Names, and Functions https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/rm_avgx_starter_boar...

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Hello Welcome to Intel forum. Please give me some time to further check with support/board team. I will get back to you with an update.
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Hello Done checking with team. For GPIO you can use LVDS or 2.5-V pin except the Transceiver pin. Refer link for HSMC Port A Pin Assignments, Schematic Signal Names, and Functions https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/rm_avgx_starter_boar...

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Thank you very much! I have already successfully used a few of the GPIOs for my purpose.

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