FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5153 Discussions

Cyclone 10GX eval board serdes pin mapping question

RBach6
Beginner
441 Views

Hi,

I designed a board with high speed adc,dac and clock on an fmc board to match with the fmc connector on the cyclone 10gx eval board. For the most part it is working good. I am running into an issue with serdes. I overlooked this part when assigning the pins that when using serdes, the clock and all the data lines need to go to the same bank. I missed this part and clock and most of the data lines are routed to bank 3A. Two of the data lines are routed to bank 3B. I am going to do another version of the board to route all the signals to bank 3A. Is there a way, I can test the other data lines for functionality in the mean time? would it be possible to use manual deserialization or a way to bypass the constraint that all the data lines need to go to the same bank? this is only temporary and I would like to test these lines, before another revision if possible. Please let me know

 

Thanks,

Ramakrishna

0 Kudos
1 Reply
SreekumarR_G_Intel
135 Views
Hello , Can you try to promote the reference clock (clock input) manually ? Here is the quartus prime setting assignment , set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to <name of toplevel reference clock input port> kindly let me know how it go ? Thank you , Regards, Sree Like
Reply