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Arria10 unpowered state issue

Indumathi
Novice
252 Views

Hi Team,

I am designing an Arria 10FPGA Board For USS 3.0 GEN2 10 G Interface. I am new to this FPGA Based Design as well as multiple processors in one board. Could you please guide me and answer the below questions.

FPGA --> Arria 10 

Part Number --> 10AX057N2F40E2SG

Current Design --> Arria 10's I/O are interfaced with other peripherals[Processor/FPGA] in the board am designing. [ In My Design Arria 10 FPGA is the main IC and it is interfaced with other SOC too].

 

1. What will happen if i plug in a USB Device when the FPGA is in an unpowered state. will the transceiver pins get damaged?

How to overcome the hot socketing limitation in Arria 10 FPGA.

As per AN 692: Power Sequencing Considerations Document the Arria10 FPGA Does not support unpowered state at hte transceiver and LVDS IO of the FPGA
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1 Solution
AminT_Intel
Employee
237 Views

Hello,

 

Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 L-tile and H-tile device transceiver pins do not support ‘Hot-Socketing.’ Fully configure the transceiver block before driving or having any activity on the Intel Cyclone 10 GX and Intel Arria 10 device transceiver pins.

We would advise not to do that in unpowered state. The Arria® 10 device dedicated transceiver pins are not subject to the same hot-socketing limitations of the general purpose I/O pins. It is OK to drive the dedicated transceiver pins during power-up and power-down sequencing of Arria 10 devices.

 

Thank you.

Amin

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2 Replies
AminT_Intel
Employee
238 Views

Hello,

 

Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 L-tile and H-tile device transceiver pins do not support ‘Hot-Socketing.’ Fully configure the transceiver block before driving or having any activity on the Intel Cyclone 10 GX and Intel Arria 10 device transceiver pins.

We would advise not to do that in unpowered state. The Arria® 10 device dedicated transceiver pins are not subject to the same hot-socketing limitations of the general purpose I/O pins. It is OK to drive the dedicated transceiver pins during power-up and power-down sequencing of Arria 10 devices.

 

Thank you.

Amin

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Glen
Beginner
114 Views

Hi,

In section 1.3.2 "Transceiver Pin Guidance for Unpowered FPGA" of AN 692 (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an692.pdf) 

It says:

"Fully configure the transceiver block before driving or having any activity on the Intel Cyclone 10 GX and Intel Arria 10 device transceiver pins."

 

We have several A10 boards inter-connected throuth XCVR (Serial Lite III). They are not powered on at the same time. XCVR pins of early powered devices may drive signals to unpowered XCVR pins of late powered devices. Will this lead to device damage? Thanks!

 

Best regards,

Glen

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