Both endpoint and root port interface simaltaniously being use on Arria 10 Soc Dev Kit

[andrewb1]

Dear Support/Expert,

I have been looking for confirmation that something like this is possible, but haven't found a clear answer, and don't want to spend time trying to get it to work if it isn't.

What i want to do with my Arria 10 SoC FPGA Development Kit Board is to have it both acting as a root port, and an endpoint, as part of the same design.

The goal would be to act as a PCIe switch, where I can present the dev board as a type 1 device (native endpoint interface), and respond to and send up stream PCIe packets from an alternate slot on the board(root port interface).

Is this possible on this board?

Thank you,

Andrew.

[KhaiChein_Y_Intel]

Hi Andrew,

The Scalable Switch Intel FPGA IP for PCIe is supported in P-tile only.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug20265.pdf

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY