FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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C5 SoC HPS to FPGA read out of on chip ram with dd

Honored Contributor II



I am using a Terrasic C5 SoCKit Development board. I am trying to read data from a On chip ram instantiated on the Qsys bus from the the HPS.  


I have created a qsys bus with a hard processor system bridge and an on chip ram and have compiled the design.  


I boot the board using the microSD setup with the linux image that came with the dev kit. I disable the bridges from the hps to the fpga , the fpga to the hps and the lightweight hps to the fpga. I then program down the FPGA image using the JTAG. When the fpga image is programmed I re-enable the bridges. I am using the insystem memory content editor to push down some test values to read back.  


I am trying to use dd to read and write to the on chip memory on the qsys bus (only reading at the moment as its not working and reading is safer).  


The command I am using is  


dd if=/dev/mem count=1 bs=512 skip=0 


I have also tried bs of 4096 and I am definately not reading the on chip ram. 


My question is, is it possible to read the fpga bus using dd and /dev/mem or am I not going to get anywhere this way? I know I can use C and write a program but for now I just want a command line setup so I can send data to and from some test interfaces.  


I am not sure what the start address/offset for the bus will be. Is this something I can set or is it a default? I dont know what the block size is either! the dd default is 512 but I have read that the page size for the linux being used is 4096 which might be completely irrelevant.  


Any help or pointers in the right direction would be appreciated!!! 




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