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5146 Discussions

Calibration failure for DDR4 EMIF in arria 10 SoC development kit

srinivasan
Beginner
620 Views
Hi,
I am getting calibration failure for DDR4 EMIF in arria 10 SoC development kit..
What is the reason for getting failure?
Can anyone give solution for error?
0 Kudos
11 Replies
yoichiK_intel
Employee
611 Views

Hi

Probably the pin location or memory parameter's are mistaken.

Please take an advantage of using the preset of targeting Arria10 SoC devkit for DDR4 EMIF example design.  This will generate 100% guaranteed functional design.  Please follow the link for the detail. 

 

https://www.intel.com/content/www/us/en/programmable/documentation/pvu1502901260167.html#mhi14401642...

srinivasan
Beginner
602 Views
Hi,
Eventhough I am selecting the same the arria 10 SoC development kit from preset...but I am getting the calibration failure..
If so possible ,can u please share your EMIF traffic gen working project...
yoichiK_intel
Employee
597 Views

Hi

Which of FGPA EMIF or HPS EMIF are you referring to ?

srinivasan
Beginner
593 Views
Hi,
Fpga EMIF for arria 10 SoC development kit
yoichiK_intel
Employee
585 Views

please try to use the attached design.  the design was created by Quartus pro 20.4 version.

srinivasan
Beginner
576 Views
Can you able share .zip file..beacaue war file it is not opening..
srinivasan
Beginner
564 Views
Whether your project created in quartus prime pro 17.1...because 20.4 lite edition no arria 10 available..only in standard edition only available...so I dnt have liscence for that...could u able share 17.1version project file..
yoichiK_intel
Employee
554 Views

Hi

Here is the design for 17.1 pro and zipped for you.

srinivasan
Beginner
548 Views
Hi,
Thanks for sharing...
But I got output for that...
If u have created user interface( Avalon-mm) for EMIF IP..if so possible can u share the file?
yoichiK_intel
Employee
537 Views

Hi

The traffic generator module is attached in the design  which interfacing to DDR4 EMIF IP via Avalon-mm.

the module path is here

qii/ip/ed_synth/ed_synth_tg/synth/ed_synth_tg.v

 

 

srinivasan
Beginner
532 Views
Hi,
Ya correct...I am asking user interface vhdl code(Avalon mm) to interface with EMIF IP

Need to remove tg and include user interface code..
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