FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5232 Discussions

Can't get DE0 nano board to boot from EPCS with NIOSII code running from SDRAM

RThie6
Beginner
678 Views

I have made several attempts to make DE0 nano boot from flash (epcs64) with a Nios II and code running from SDRAM. In the mean time I have tried all tutorials, every trick posted over the several years. Using Quartus lite 18.1. Would somebody be so kind to just help or post a bare example (and maybe workflow) of a DE0 nano board booting from EPCS and then run code in SDRAM. ps. I know the hardware is functioning. But the code just won't load. Many thanks in advance

0 Kudos
1 Solution
Fawaz_J_Intel
Employee
353 Views
8 Replies
Fawaz_J_Intel
Employee
353 Views

Hello,

I have done this long time ago. You need to maintain two important things:

1- The clock that feeds the SDRAM should be shifted around -3 nano seconds.

2- Use Older Quartus Programmer version instead of 18.1, for example 15.0

 

Page 11 of this document shows the PLL time shift to handle the SDRAM timing issue:

ftp://ftp.intel.com/Pub/fpgaup/pub/Intel_Material/17.0/Tutorials/Verilog/DE0-Nano/Using_the_SDRAM.pd...

 

This document below, shows how to program the EPCS of DE0-nanop

ftp://ftp.intel.com/Pub/fpgaup/pub/Intel_Material/17.0/Tutorials/DE0-Nano/Using_DE0-Nano_Flash.pdf

 

Thanks

 

RThie6
Beginner
353 Views

Many thanks for your reply and links. I can perfectly run the program in SDRAM form the debugger (eclipse). I can perfectly make a bootable epcs64 system when nios is running from SRAM (and NOT SDRAM). It's the combination of getting it to boot from EPC and rund code/data from SDRAM that is the issue. I know the hardware boots from EPCS.. but for some reason the code isn't loaded into Sram or not booted... all parameters are set correct according to Intel manual... So problem persists

RThie6
Beginner
353 Views

Many thanks for your reply and links. I can perfectly run the program in SDRAM form the debugger (eclipse). I can perfectly make a bootable epcs64 system when nios is running from SRAM (and NOT SDRAM). It's the combination of getting it to boot from EPC and rund code/data from SDRAM that is the issue. I know the hardware boots from EPCS.. but for some reason the code isn't loaded into Sram or not booted... all parameters are set correct according to Intel manual... So problem persists

Fawaz_J_Intel
Employee
353 Views

Hello,

I have sent you an email for a debug session.

 

thank you

Fawaz_J_Intel
Employee
353 Views

Hello,

My apologize for the late reply. I was looking for a DE0 nano board to test the design, and luckily, I found one. I could test the design on board and its booing from EPCS without any issue.

I will attach the design to help you settle the issue.

 

Thank you

BXia
Novice
19 Views

Hi Fawaz,

 

I tested the attached project with my DE0-Nano board, I had a error when using the Flash Programmer to program the EPCS device, could you help checking the issue? I attached the error information here.

 

By the way, could you teach me how you generated the .jic file for this project?

 

Thanks in advance.

flash_error.jpg

Fawaz_J_Intel
Employee
354 Views
posted a file.
RThie6
Beginner
353 Views

This design works indeed. Thanks.

Reply