Clocking Network (Quartus prime pro 20.2)

[Shubhall]

Hi,

I generated low latency MAC example design from the Quartus prime pro 20.2(screenshot attached for reference - 10G_base_R_design_example.png) ; in the ATX pll IP for PHY,  I did not choose any option related to MCGB, bonding or xN clocking (screenshot attached for reference - MCGB_default_reference.png) . But I assigned the clock from 1E bank (PIN_AG29) directly as reference clock for my SFP transceiver (present in 1C bank - PIN_AW33 for tx and PIN_AU33 for Rx). 

Generating the build was successful. Even though I am taking reference clock from some other bank without even enabling xN clocking or bonding or MCGB, I did not get any error. I am confused how is it happening. Is this version of Quartus routes to clock intelligently (inter bank clocking). 

Kindly help I am confused. My device and design details are as follows -

Development kit  - Arria 10 SX SOC development kit (https://www.intel.in/content/www/in/en/products/details/fpga/development-kits/arria/10-sx.html)

Board  - 10AS066N3F40E2SG

Schematic diagram referred - Arria 10 SOC revC (a10_soc_devkit_03_31_2016.pdf)

Kindly let me know if more info required from my side.

Thank you

Regards

Shubhangi

[Shubhall]

I am getting this warning while generating .sof 

ATX/FPLL < dut_inst|wrapper_inst|atx_pll_inst|altera_xcvr_atx_pll_ip_inst|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst > is not placed in the same bank as the reference clock.

Can I ignore this warning or do I have to compulsory use the bonded/xN clocking?

[Caguicla_Intel]

Hello Shubhall,

Thank you for posting in Intel Ethernet Communities. 

Since your query involves Field-programmable gate array (FPGA), please be informed that this will be best answered by our FPGA support team. We will help you to move this post to the designated team for further assistance. Please feel free to contact us if you need assistance from Ethernet support team.

Best regards,

Crisselle C.

Intel® Customer Support

[Kshitij_Intel]

Hi Shubhall,

For the best jitter performance, Intel recommends using a reference clock within the same bank as the transceiver PLL (ATX PLL, fPLL) that the reference clock is driving.

If possible, please put the ATX PLL or fPLL in the same bank as reference clock in Assignment Editor.

Thank you

Kshitij Goel

[Shubhall]

okay ... 

[Kshitij_Intel]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘ https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you

Kshitij Goel